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| Name | 3D Stacked Transistors: Improving Area By Building Upward | Intel Technology |
| Video Uploader | Video From Intel Technology |
| Upload Date | This Video Uploaded At 11-12-2021 16:32:42 |
| Video Discription | The pursuit of increased performance and transistor density will be realized not just by making transistors smaller, but also through novel designs and structures. Intel Component Research Engineer, Marko Radosavljevic, uses augmented reality to walk through several years of Intel breakthroughs demonstrating the development of 3D stacking techniques that will be able to reduce a chip’s logic footprint. Learn more: https://intel.ly/3EPDvG6 Subscribe now to Intel Technology on YouTube: https://intel.ly/3P9BA7x About Intel Technology: Intel has always been at the forefront of developing exciting new technology for business and consumers including emerging technologies, data center servers, business transformation, memory and storage, security, and graphics. The Intel Technology YouTube channel is a place to learn tips and tricks, get the latest news, and watch product demos from both Intel and our many partners across multiple fields. Connect with Intel Technology: Visit Intel Technologies WEBSITE: https://intel.ly/IntelTechnologies Follow Intel Technology on TWITTER: https://twitter.com/IntelTech 3D Stacked Transistors: Improving area by building upward | Intel Technology https://www.youtube.com/inteltechnology |
| Category | Science & Technology |
| Tags | 3d stacked transistors improving area by building upward | marko radosavljevic | 3d stacking techniques | transistors | augmented reality | transistor density |
